1. Field of the Invention
The present invention relates to the field of microprocessors and microprocessor-based devices, such as flash memories; more particularly, the present invention relates to a method and apparatus for adjusting a clock period for a particular cycle dependent on one or more instructions to be performed during that cycle.
2. Description of Related Art
Microprocessors (including microcontrollers) execute instructions at a speed governed by the period of a clock signal. The performance of a microprocessor is generally increased by reducing the period (increasing the frequency) of the clock signal. As the clock period is reduced, the time allocated to perform each step of an instruction is reduced, thereby increasing performance. If the delay of the circuit used to perform a particular step of an instruction (execution time) is longer than the clock period, the results of that step will not be completed before the end of the clock period, thereby leading to malfunction. Thus, the minimum clock period is limited by the maximum execution time of any step of any instruction in the instruction set.
In a pipelined microprocessor, instructions are performed in multiple steps, such as a fetch cycle (in which instructions are retrieved from a memory), a decode cycle (in which instructions are decoded), one or more execute cycles (in instructions are executed) and a writeback cycle (in which results of the instructions are written in the memory). At a given time, one instruction may be fetched, a second instruction may be decoded, a third instruction may be executed, and the result of a fourth instruction may be written back. Since each of these steps are performed during a period of the clock signal (a clock cycle), the minimum clock period is the longest execution time of any step for all the instructions in the microprocessor's instruction set.
If the clock period is shorter than the longest execution time, the steps of instructions that have execution times greater than the clock period would not be completed in a clock cycle. If such an instruction is executed with a clock period that is not long enough to allow all its steps to complete, the microprocessor malfunctions.
The clock period is set at the longest execution time to allow the microprocessor time to complete all its steps but to reduce the time after the execution of the last step but before the end of the clock period. If the clock period is longer than the longest execution time, performance is reduced. In such a case, even the step with the longest execution time is completed a time before the end of the period. Thus, the circuit performing that step is idle for that time.
The steps of instructions are generally split up so that the execution times are approximately the same. If some execution times are much longer than the others, the clock period is set to be at the longest execution time, which is much longer than the others. Thus, when a circuit executes steps with shorter execution times, it is idle for much of the clock period.
If microprocessor instruction set includes an instruction having a step with an execution time that is larger than the longest execution time of any step for all the rest of the instructions in the microprocessor instruction set, the step is often split into two or more steps such that that step has an execution time that more closely matches the others. For example, if the execution time for a step of one instruction is 19 nanoseconds (ns) and the longest execution time of any step for all the rest of the instructions in the microprocessor instruction set is 10 ns, the minimum period of the microprocessor is 19 ns. If the step having an execution time of 19 ns is split into two steps each having an execution time of 9.5 ns, the minimum period of the microprocessor is reduced from 19 ns to 10 ns. In such a case, the performance increase associated with the reduction in the minimum period (19 ns to 10 ns) generally outweighs the performance decrease associated with the single 19 ns step that is split into two 10 ns steps (19 ns to 20 ns latency).
In some cases, splitting a step into two or more steps may not be desirable. For example, if the execution time for a step of one instruction is 12 nanoseconds (ns) and the longest execution time of any step for all the rest of the instructions in the microprocessor's instruction set is 10 ns, the minimum period of the microprocessor is 12 ns. If the step having an execution time of 12 ns is split into two steps each having an execution time of 6 ns, the minimum period of the microprocessor is reduced to 10 ns. In such a case, the performance increase associated with the reduction in the minimum period (12 ns to 10 ns) may not outweigh the performance decrease associated with the 12 ns step that is split into two 10 ns steps (12 ns to 20 ns delay).
What is needed is a method and apparatus to reduce the idle time of execution units in a microprocessor.